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Re: Few questions about porting Linux to SMP86xx boards

To: Oleg Kolosov <bazurbat@gmail.com>
Subject: Re: Few questions about porting Linux to SMP86xx boards
From: "Maciej W. Rozycki" <macro@linux-mips.org>
Date: Tue, 3 Feb 2015 11:39:20 +0000 (GMT)
Cc: Måns Rullgård <mans@mansr.com>, Kevin Cernekee <cernekee@chromium.org>, Linux MIPS Mailing List <linux-mips@linux-mips.org>
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On Tue, 3 Feb 2015, Oleg Kolosov wrote:

> >>> 1. They (Sigma Designs) have overridden __fast_iob which is identical to
> >>> the default one except for one line:
> >>> ...
> >>
> >> I do not have any direct experience with these SoCs, but you might
> >> want to look at the memory map to try to figure this one out.  i.e. if
> >> __fast_iob() normally performs an uncached dummy read from the first
> >> word of physical memory, does the address need to be adjusted by 64MB
> >> on the Sigma chips because system memory (or the memory allocated to
> >> the Linux application processor) starts at PA 0x0400_0000 instead of
> >> 0x0000_0000?
> >>
> >> That theory would also explain why the exception vectors were adjusted
> >> by the same offset.
> > 
> > The 86xx has two DRAM controllers mapped with 1GB windows at 0x8000_0000
> > and 0xc000_0000, and also with 256MB windows at 0x1000_0000 and 0x2000_0000.
> > To complicate matters, CPU physical addresses starting at 0x04000000 are
> > subjected to a set of remapping registers translating 6 blocks of 64MB
> > to an arbitrary (64MB-aligned) bus address (not that these addresses
> > overlap with the low mappings of the DRAM controllers).  The obvious way
> > to support this would be to simply set these registers to an identity
> > mapping and use highmem for anything that doesn't fit the low windows.
> > Obviously, they didn't do that.
> > 
> 
> Thanks for the explanations! This is really useful.

 For the record -- the exact address `__fast_iob' reads from does not 
really matter, all it has to guarantee is no side effects on read access.  
Using the base of KSEG1 was therefore a natural choice for legacy MIPS 
processors that set the architecture back at the time this code was added, 
as the presence of exception vectors there guaranteed this area of the 
address space behaved like RAM so the same location did for any system.

 With the introduction of revision 2 of the MIPS architecture the CP0 
EBase register was added and consequently there is no longer a guarantee 
that exception vectors reside at the base of KSEG1.  Using the value read 
from CP0.EBase to determine a usable address might therefore be a better 
idea, although the current revision of the MIPS architecture specification 
that includes segmentation control makes it a bit complicated.  Using a 
dummy page mapped uncached instead might work the best.

  Maciej

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