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Re: [PATCH V2 4/8] MIPS: Add NUMA support for Loongson-3

To: Ralf Baechle <>
Subject: Re: [PATCH V2 4/8] MIPS: Add NUMA support for Loongson-3
From: David Daney <>
Date: Tue, 03 Jun 2014 16:47:52 -0700
Cc: Huacai Chen <>, John Crispin <>, "Steven J. Hill" <>, Aurelien Jarno <>,, Fuxin Zhang <>, Zhangjin Wu <>
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On 06/03/2014 03:47 PM, Ralf Baechle wrote:
--- a/arch/mips/include/asm/addrspace.h
+++ b/arch/mips/include/asm/addrspace.h
@@ -51,8 +51,14 @@
   * Returns the physical address of a CKSEGx / XKPHYS address
  #define CPHYSADDR(a)          ((_ACAST32_(a)) & 0x1fffffff)
+#ifndef CONFIG_NUMA
  #define XPHYSADDR(a)          ((_ACAST64_(a)) &                   \
+#define XPHYSADDR(a)           ((_ACAST64_(a)) &                   \
+                                _CONST64_(0x0000ffffffffffff))

The mask in XPHYSADDR is a function of the processor architecture, not
imlementation, not NUMA.  The latest version of the MIPS architecture
permits PABITS to be as large as 49 bits, so the mask should be
0x0001ffffffffffff.  Always.

diff --git a/arch/mips/include/asm/sparsemem.h 
index d2da53c..c001a90 100644
--- a/arch/mips/include/asm/sparsemem.h
+++ b/arch/mips/include/asm/sparsemem.h
@@ -11,7 +11,12 @@
  # define SECTION_SIZE_BITS    28
+#define MAX_PHYSMEM_BITS       48
  #define MAX_PHYSMEM_BITS      35

Essentially the same comment as for XPHYSADDR above.

Are you saying to change it to 49 unconditionally for all configurations?

That would work for OCTEON too, where we have had to increase it to 42.

What are the implications for kernel data structures if this is set many orders of magnitude greater than the actual number of bits used on a system?


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