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Re: mips octeon memory model questions

To: Peter Zijlstra <>
Subject: Re: mips octeon memory model questions
From: Linus Torvalds <>
Date: Tue, 4 Feb 2014 11:16:58 -0800
Cc: David Daney <>, Ralf Baechle <>, "" <>, linux-mips <>, Linux Kernel Mailing List <>, Paul McKenney <>, Will Deacon <>
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On Tue, Feb 4, 2014 at 11:05 AM, Peter Zijlstra
>> So writes move down, not up.
> Right, but the ll-sc store might move down over a later store.

Unlikely. The thing is, in order for the sc to succeed, it has to
already have hit the cache coherency domain (or at least reserved it -
ie maybe the value is not actually *in* the cache, but the sc needs to
have gotten exclusive access to the cacheline).

So just how do you expect a later store (that is *after* the
conditional branch that tests the result of the sc) to move up before

I'm not saying it's physically impossible: speculation is always
possible. But it would require some rather clever speculative store
buffers or caches and killing of same when mispredicted. Which is
actually fairly unlikely, since stores are seldom - if ever - in the
critical path. IOW, "lots and lots of effort for very little gain".

So I'm personally quite willing to believe that a
sc+conditional-branch+st is quite well ordered without any extra
barriers. I'd be more worried about *reads* moving up past the sc
("doesn't reorder reads" to me would imply not moving across the "ll"
part, but it's quite likely that the "sc" actually counts as both a
read and a write).

Without any visible documentation (see aforementioned "clown company"
comment) all of this is obviously just pure speculation.


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