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mips octeon memory model questions

To: David Daney <>, Ralf Baechle <>
Subject: mips octeon memory model questions
From: Peter Zijlstra <>
Date: Tue, 4 Feb 2014 19:41:50 +0100
Cc:,,, Paul McKenney <>, Will Deacon <>, Linus Torvalds <>
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Hi all,

I have a number of questions in regards to commit 6b07d38aaa520ce.

Given that the octeon doesn't reorder reads; the following:

"      sync
       ll ...
       sc ...

  The second SYNC was redundant, but harmless.  "

Still doesn't make sense, because if we need the first sync to stop
writes from being re-ordered with the ll-sc, we also need the second
sync to avoid the same.

   STORE a
   LL-SC b
   (not a sync)
   STORE c

What avoids this becoming visible as:



Then there is:

"       syncw;syncw

    Has identical semantics to the first sequence, but is much faster.
    The SYNCW orders the writes, and the SC will not complete successfully
    until the write is committed to the coherent memory system.  So at the
    end all preceeding writes have been committed.  Since Octeon does not
    do speculative reads, this functions as a full barrier."

Read Documentation/memory-barrier.txt:TRANSITIVITY, the above doesn't
sound like syncw is actually multi-copy atomic, and therefore doesn't
provide transitivity, and therefore is not a valid sequence for
operations that are supposed to imply a full memory-barrier.

Please as to explain.

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