[Top] [All Lists]

[PATCH 0/5] MIPS: Add support for OCTEON III based SoCs.

Subject: [PATCH 0/5] MIPS: Add support for OCTEON III based SoCs.
From: David Daney <>
Date: Mon, 29 Jul 2013 15:06:59 -0700
Cc: David Daney <>
Dkim-signature: v=1; a=rsa-sha256; c=relaxed/relaxed;; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=ozO4/Zf2XfLznYeMDf8q+a4n5jlDKihVzw2fn5DNFhQ=; b=mb22FlpcLnrwarn33fngazxROouqauwlKjuUIFK75Q8HN55Z/p6Qpmr7eR+0/O8iXS hswJxnqJSdnrjKrA1Y95dW7EEwMXyFHFFpt+vEzPs9jNeSKXkxxe1/gYI6e6AHIXpT+n cpsT3LEIXykEXR54i5SZN6nFotOLgOtHO84lyB38vxFM5LykbFG9j+DLCHN7mwp9vYBw H7YMk1qG5YYS49Klkh0tMEl4GzBVaEBQUJwcM8qqChf9IOsNCUlSCirJ+3mJNXvAXW1j SBPaY2j8mng7NIryuWtWtS/lspptV5oIJEMK9QqVF/SQjiIn4lN6lcxsw8Qxsx3FSLga ZySA==
List-archive: <>
List-help: <>
List-id: linux-mips <>
List-owner: <>
List-post: <>
List-software: Ecartis version 1.0.0
List-subscribe: <>
List-unsubscribe: <>
Original-recipient: rfc822;
From: David Daney <>

These patches add minimal support for SoCs in the OCTEON III family.
In many respects, they are similar to OCTEON II, but with larger cache
and FPU.  FPU support comes later...

David Daney (5):
  MIPS: Add CPU identifiers for more OCTEON family members.
  MIPS: Probe for new OCTEON CPU/SoC types.
  MIPS: Use r4k_wait for OCTEON3 CPUs.
  MIPS: Generate OCTEON3 TLB handlers with the same features as
  MIPS: OCTEON: Set L1 cache parameters for OCTEON3 CPUs.

 arch/mips/include/asm/cpu.h  |  5 ++++-
 arch/mips/kernel/cpu-probe.c |  7 +++++++
 arch/mips/kernel/idle.c      |  1 +
 arch/mips/mm/c-octeon.c      | 14 ++++++++++++++
 arch/mips/mm/tlbex.c         |  2 ++
 5 files changed, 28 insertions(+), 1 deletion(-)


<Prev in Thread] Current Thread [Next in Thread>