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Re: [PATCH 1/2] netdev: octeon_mgmt: Correct tx IFG workaround.

To: Joe Perches <>
Subject: Re: [PATCH 1/2] netdev: octeon_mgmt: Correct tx IFG workaround.
From: David Daney <>
Date: Wed, 19 Jun 2013 18:28:42 -0700
Cc:, "David S. Miller" <>,, David Daney <>
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On 06/19/2013 06:08 PM, Joe Perches wrote:
On Wed, 2013-06-19 at 17:40 -0700, David Daney wrote:
From: David Daney <>

The previous fix was still too agressive to meet ieee specs.  Increase
to (14, 10).
diff --git a/drivers/net/ethernet/octeon/octeon_mgmt.c 
@@ -1141,10 +1141,13 @@ static int octeon_mgmt_open(struct net_device *netdev)
                /* For compensation state to lock. */
                ndelay(1040 * NS_PER_PHY_CLK);

-               /* Some Ethernet switches cannot handle standard
-                * Interframe Gap, increase to 16 bytes.
+               /* Default Interframe Gaps are too small.  Recommended
+                * workaround is.
+                *
+                * AGL_GMX_TX_IFG[IFG1]=14
+                * AGL_GMX_TX_IFG[IFG2]=10

Why isn't the TX IFG just 96 bit times?

I don't have a full understanding of how the transistors are wired up on the chip, so I cannot accurately answer your question. But I can say that after I empirically found the previous values to get the thing to work, the hardware designers independently found that the values supplied in this patch are required to achieve industry standard IFGs with this hardware.

I'm also confused a bit here by the difference between the
bsd implementation and yours.

  2628  * * Programming IFG1 and IFG2.
  2629  *
  2630  *   For half-duplex systems that require IEEE 802.3 compatibility, IFG1 
  2631  *   be in the range of 1-8, IFG2 must be in the range of 4-12, and the
  2632  *   IFG1+IFG2 sum must be 12.
  2633  *
  2634  *   For full-duplex systems that require IEEE 802.3 compatibility, IFG1 
  2635  *   be in the range of 1-11, IFG2 must be in the range of 1-11, and the
  2636  *   IFG1+IFG2 sum must be 12.
  2637  *
  2638  *   For all other systems, IFG1 and IFG2 can be any value in the range 
  2639  *   1-15.  Allowing for a total possible IFG sum of 2-30.
  2640  *
  2641  * Additionally reset when both MIX0/1_CTL[RESET] are set to 1.

The advice in that particular comment in the BSD source code has been found to be incorrect, that is why we are overriding the default value of this register in the first place.

-               cvmx_write_csr(CVMX_AGL_GMX_TX_IFG, 0x88);
+               cvmx_write_csr(CVMX_AGL_GMX_TX_IFG, 0xae);


I don't have a datasheet.  Is one available?

I don't believe the datasheets are publicly available, but they do exist. If you feel you have a compelling reason to have one, and don't mind jumping through hoops, you could contact me privately.

David Daney

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