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Re: prom start

To: Ralf Baechle <>
Subject: Re: prom start
From: folkert <>
Date: Sun, 10 Feb 2013 17:43:45 +0100
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Reply-by: Sat Feb 9 18:32:07 CET 2013
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> > Is this mailing list also meant for generic mips questions? (if not: any
> > suggestions for one that is?)
> > 
> > If so: I'mm experimenting a bit with mips, specifically on SGI hardware
> > (Indigo). Now it seems all mips systems have the prom at 0xbfc00000. But
> > how does it start? The first 0x3c0 bytes seem to be nonsense. Somewhere
> > on the web I found that 0xbfc00884 is the starting point but after
> > single stepping 5 instructions, the program counter jumps to 0x00000000
> > so I don't think that's the right one either. Also, reading the first 4
> > bytes from bfc00000 and using that as a pointer seems to be invalid too:
> > 0bf000f0.
> > Anyone with insights regarding the booting of the prom on sgi systems?
> All MIPS processors start execution at 0xbfc00000 after a hardware reset
> or NMI.  0xbfc00884 is not an address that has any specific meaning in
> the processor architecture itself.  I think it's being used in the GXemul
> documentation just for sake of an example.

Yes that seems to be the case. If I start at 0xbfc00000 it looks

> If your disassembler defaults to like MIPS I / R3000 it won't disassemble
> all instructions for the MIPS III R4000 processor.  I'd expect some
> cache initialization code right at 0xbfc00000 and that could would be
> affected.

I'm not entirely sure yet. My D-A (well, an emulator to be honest)
implements the mips as described in MD00086 (by Mips technologies) of
June 2003 and at the bottom that document acknowledges the MIPS R3000,
4000, 5000 and 10000.

It's really fun to do, writing that mips code. All new to me. I'm at the
point that it emulates enough of the prom that it reaches points where
it gets even more interesting: undocumented hardware (0xbfa00030 and
0xbfa01004 anyone?) and fiddeling with COP0.

Folkert van Heusden

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