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[PATCH] Malta: Remove RTC Data Mode bootstrap breakage

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Subject: [PATCH] Malta: Remove RTC Data Mode bootstrap breakage
From: "Maciej W. Rozycki" <>
Date: Thu, 13 Sep 2012 21:23:25 +0100
Cc: Ralf Baechle <>
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User-agent: Alpine 1.10 (DEB 962 2008-03-14)
 YAMON requires and enforces the RTC Data Mode (Register B, DM bit) to 
binary, that is the bit is set every time the board goes through the 
firmware bootstrap sequence.  Likewise its calendar manipulation commands 
interpret or set the RTC registers unconditionally as binary, never 
actually checking what the value of the DM bit is, under the (correct) 
assumption that it has been previously set, to indicate the binary mode.

 A change to Linux a while ago however introduced a platform-specific 
tweak that clears that bit and therefore forces the data mode to BCD.  
This causes clock corruption and misinterpretation that has to be fixed up 
by user-mode tools in system startup scripts as the initial clock is often 
incorrect according to the BCD interpretation forced.

 This change removes the hack; a comment included refers to alarm code, 
but even if it was broken at one point by requiring the BCD mode, it 
should have been trivially corrected and even if not, given how rarely the 
alarm feature is used, that was not really a reasonable justification to 
break the system clock that is indeed used by virtually everything.  And 
either way the alarm code has been since fixed anyway.

Signed-off-by: Maciej W. Rozycki <>

 Please apply -- this ends a long battle trying to track down where the 
annoying clock corruption has come from.


diff --git a/arch/mips/mti-malta/malta-platform.c 
index 4c35301..80562b8 100644
--- a/arch/mips/mti-malta/malta-platform.c
+++ b/arch/mips/mti-malta/malta-platform.c
@@ -138,11 +138,6 @@ static int __init malta_add_devices(void)
        if (err)
                return err;
-       /*
-        * Set RTC to BCD mode to support current alarm code.
-        */
        return 0;

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