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Re: [PATCH] MIPS: Fix for warning from FPU emulation code

To: Jayachandran C <>, David Daney <>
Subject: Re: [PATCH] MIPS: Fix for warning from FPU emulation code
From: Ralf Baechle <>
Date: Wed, 15 Aug 2012 19:42:19 +0200
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On Tue, Aug 14, 2012 at 09:33:40PM +0530, Jayachandran C wrote:

> The default implementation of 'cpu_has_fpu' macro calls
> smp_processor_id() which causes this warning to be printed when
> preemption is enabled:
> [    4.664000] Algorithmics/MIPS FPU Emulator v1.5
> [    4.676000] BUG: using smp_processor_id() in preemptible [00000000] code: 
> ini
> [    4.700000] caller is fpu_emulator_cop1Handler+0x434/0x27b8
> Use 'raw_cpu_has_fpu' macro in cop1_64bit() instead of 'cpu_has_fpu'
> to fix this. Fix suggested by Ralf Baechle <>

I think your patch was 34K-ly correct but I never managed to convince
myself that it really was and anyway, cpu_has_fpu expands into too much
code for the runtime detection case.  With below patch all platforms I
tested have either unchanged or smaller code size depending on the
kernel configuration.

The whole problem got introduced in November 2009 by
af1d2af877ef6c36990671bc86a5b9c5bb50b1da (lmo) [MIPS: Fix emulation of
64-bit FPU on 64-bit CPUs.] rsp.  da0bac33413b2888d3623dad3ad19ce76b688f07
( [MIPS: Fix emulation of 64-bit FPU on FPU-less 64-bit CPUs.]
in 2.6.32.


 arch/mips/math-emu/cp1emu.c | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index a03bf00..47c77e7 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -171,16 +171,17 @@ static int isBranchInstr(mips_instruction * i)
  * In the Linux kernel, we support selection of FPR format on the
  * basis of the Status.FR bit.  If an FPU is not present, the FR bit
  * is hardwired to zero, which would imply a 32-bit FPU even for
- * 64-bit CPUs.  For 64-bit kernels with no FPU we use TIF_32BIT_REGS
- * as a proxy for the FR bit so that a 64-bit FPU is emulated.  In any
- * case, for a 32-bit kernel which uses the O32 MIPS ABI, only the
- * even FPRs are used (Status.FR = 0).
+ * 64-bit CPUs so we rather look at TIF_32BIT_REGS.
+ * FPU emu is slow and bulky and optimizing this function offers fairly
+ * sizeable benefits so we try to be clever and make this function return
+ * a constant whenever possible, that is on 64-bit kernels without O32
+ * compatibility enabled and on 32-bit kernels.
 static inline int cop1_64bit(struct pt_regs *xcp)
-       if (cpu_has_fpu)
-               return xcp->cp0_status & ST0_FR;
-#ifdef CONFIG_64BIT
+#if defined(CONFIG_64BIT) && !defined(CONFIG_MIPS32_O32)
+       return 1;
+#elif defined(CONFIG_64BIT) && defined(CONFIG_MIPS32_O32)
        return !test_thread_flag(TIF_32BIT_REGS);
        return 0;

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