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Re: [PATCH] MIPS: Kernel hangs occasionally during boot.

To: Ralf Baechle <>
Subject: Re: [PATCH] MIPS: Kernel hangs occasionally during boot.
From: "Gleb O. Raiko" <>
Date: Wed, 09 Nov 2011 15:26:32 +0400
Cc: Al Cooper <>,,
In-reply-to: <>
Organization: NIISI RAN
References: <y> <> <> <> <>
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On 09.11.2011 14:34, Ralf Baechle wrote:
Hmm...  Looking at the R4000 manual which generall has the longest
pipeline hazards, mtc0 gets executed at stage 7, interrupts get sampled
at stage 3 meaning there is a (7 - 3 - 1) = 3 cycles hazard.  Does
that one statisfy your constraints?  Or are additional cycles needed
for a hazard that's generated outside of the CPU's pipeline?
In fact, current back_to_back_hazard is more than enough for cpus I deal with. I guess, required time to wait equals number of stages between EX (or RD) and WB stages for modern cpus, because CP0 CAUSE is updated during WB nowadays.

I suspect, the time required to update internal counter logic for original r4k might be bigger though. At least old code waited 12 cycles (4*irq_disable_hazard which is 3 for r4k). Perhaps, we should keep this code and insert the same amount of nops for old cpus at least.


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