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Re: about udelay in mips

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Subject: Re: about udelay in mips
From: loody <>
Date: Sun, 16 Jan 2011 22:38:47 +0800
Cc: Linux MIPS Mailing List <>
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hi wu, winfred:
Thanks for your reply ;)
2011/1/14 wu zhangjin <>:
> On Thu, Jan 13, 2011 at 6:02 PM, loody <> wrote:
>> hi all:
>> If i trace source in the correct place, I found udelay(100) is
>> implemented as a loop which decrease 1 per iteration until the count,
>> 100, as 0.
>> What makes me confused is since the speed of cpus are different and
>> that will make udelay not precise on different platform, right?
> Yeah, it may be not precise, so, some processors, like Cavium octeon
> have added their own timestamp register based delay functions, please
> refer to:
> arch/mips/cavium-octeon/csrc-octeon.c
> The delay_tsc() for X86 defined in arch/x86/lib/delay.c is similar.
> But both of them are 64bit timestamp registers.
> We can also apply similar method to add the precise delays for the
> other CPUs, but we may need to take extra notice:
> 1. If the CPU only provides 32bit timestamp registers(e.g R4K MIPS),
> overflow should be considered.
> 2. If the CPU support dynamic CPU frequency and the frequency of the
> timestamp binds to the CPU's frequency, the scaled down timestamp
> should be converted to the real timestamp.
below is the formula about calculating the delay
(us  *   0x000010c7   *   HZ   *   lpj   )) >> 32)
I cannot figure out why we need to multiply 0x10c7, and what lpj mean?
Does lpj mean if jiffies increase 1, how many "subu    %0, 1" may need?

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