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Re: [PATCH resend 5/9] MIPS: sync after cacheflush

To: "Gleb O. Raiko" <>
Subject: Re: [PATCH resend 5/9] MIPS: sync after cacheflush
From: Ralf Baechle <>
Date: Tue, 19 Oct 2010 10:17:30 +0100
Cc: Kevin Cernekee <>, Shinya Kuribayashi <>,,,
In-reply-to: <>
Original-recipient: rfc822;
References: <17ebecce124618ddf83ec6fe8e526f93@localhost> <17d8d27a2356640a4359f1a7dcbb3b42@localhost> <> <> <> <>
User-agent: Mutt/1.5.21 (2010-09-15)
On Tue, Oct 19, 2010 at 12:54:33PM +0400, Gleb O. Raiko wrote:

> On 18.10.2010 23:41, Kevin Cernekee wrote:
> >I have not been able to find any official statement from MIPS that
> >says that CACHE + SYNC should be used, but that seems like the most
> >intuitive way to implement things on the hardware side.
> Indeed, both Architecture for Programmers in Vol. 2 describing
> instruction sets not so clearly say that sync is needed after cache.
> For example, documents with rev. 2.62, p. 92 (for MIPS32 ISA) or p.
> 96 (for MIPS64).

The MIPS32 BIS v2.6 spec says on page 92:

  "The CACHE instruction and the memory transactions which are sourced by
   the CACHE instruction, such as cache refill or cache writeback, obey
   the ordering and completion rules of the SYNC instruction."

That's not as clearly spelt out as one would like but it seems to imply
that only reads/writes preceeding the CACHE instruction are guaranteed
to have completed that is the last CACHE instruction that was executed
may still be incomplete.

> Considering whether just sync enough I'd like to note some boxes may
> implement dma master and slave blocks to be unsynchronized.
> Also,there may be write buffers somewhere in the path between cpu,
> memory, and even a dma master.
> BTW, we have plat_extra_sync_for_device which has appropriate name
> but invented to do things before cache flush. :-) It seems we need
> another one which will do something after.


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