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Re: [PATCH resend 5/9] MIPS: sync after cacheflush

To: Ralf Baechle <>
Subject: Re: [PATCH resend 5/9] MIPS: sync after cacheflush
From: Kevin Cernekee <>
Date: Mon, 18 Oct 2010 12:41:20 -0700
Cc: Shinya Kuribayashi <>,,
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On Mon, Oct 18, 2010 at 12:19 PM, Ralf Baechle <> wrote:
> I'm trying to get a statement from the MIPS architecture guys if the
> necessity to do anything beyond a cache flush is an architecture violation.

IMO such a requirement would be unnecessarily strict.  Larger flushes
(e.g. page at a time) tend to benefit from some form of pipelining or
write gathering.  Forcing the processor to flush exactly 32 bytes at a
time, synchronously, could really slow things down and thrash the
memory controller.

I have not been able to find any official statement from MIPS that
says that CACHE + SYNC should be used, but that seems like the most
intuitive way to implement things on the hardware side.

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