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Re: Question about Context register in TLB refilling

To: Kevin Cernekee <>
Subject: Re: Question about Context register in TLB refilling
From: "Maciej W. Rozycki" <>
Date: Sun, 17 Oct 2010 20:33:24 +0100 (BST)
Cc: "wilbur.chan" <>, Linux MIPS Mailing List <>
In-reply-to: <>
Original-recipient: rfc822;
References: <> <>
User-agent: Alpine 2.00 (LFD 1167 2008-08-23)
On Sun, 17 Oct 2010, Kevin Cernekee wrote:

> > 1) In linux ,esspecially in TLB refilling,  is Context[PTEBase] used
> > to store cpuid? (refer to build_get_pgde32 in tlbex.c)
> On 32-bit systems, PTEBase stores a byte offset that can be added to
> &pgd_current[0].  i.e. smp_processor_id() * sizeof(unsigned long)
> So the TLB refill handler can find pgd for the current CPU using code
> that looks something like this:
>    0:   401b2000        mfc0    k1,c0_context
>    4:   3c1a8054        lui     k0,0x8054
>    8:   001bddc2        srl     k1,k1,0x17
>    c:   035bd821        addu    k1,k0,k1
> ...
>   14:   8f7b5008        lw      k1,20488(k1)
> where pgd_current is at 0x8054_5008, and PTEBase is 0, 4, 8, 12, ...

 It has been always making me wonder (though not as much to go and dig 
through our code ;) ) why Linux is uncapable of using the value presented 
by the CPU in the CP0 Context register as is, or perhaps after a trivial 
operation such as a left-shift by a constant number of bits (where the 
size of the page entry slot assumed by hardware turned out too small).  
There should be no need to add another constant as in the piece of code 
you have quoted -- this constant should already have been preloaded to 
this register when switching the context the last time.  The design of the 
TLB refill exception in the MIPS Architecture has been such as to allow 
this register to be readily used as an address into the page table.  


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