On Thu, May 06, 2010 at 11:26:57PM -0600, Shane McDonald wrote:
> In the FPU emulator code of the MIPS, the Cause bits of the FCSR
> register are not currently writeable by the ctc1 instruction.
> In odd corner cases, this can cause problems. For example,
> a case existed where a divide-by-zero exception was generated
> by the FPU, and the signal handler attempted to restore the FPU
> registers to their state before the exception occurred. In this
> particular setup, writing the old value to the FCSR register
> would cause another divide-by-zero exception to occur immediately.
> The solution is to change the ctc1 instruction emulator code to
> allow the Cause bits of the FCSR register to be writeable.
> This is the behaviour of the hardware that the code is emulating.
> This problem was found by Shane McDonald, but the credit for the
> fix goes to Kevin Kissell. In Kevin's words:
> I submit that the bug is indeed in that ctc_op: case of the emulator. The
> Cause bits (17:12) are supposed to be writable by that instruction, but the
> CTC1 emulation won't let them be updated by the instruction. I think that
> actually if you just completely removed lines 387-388 [...]
> things would work a good deal better. At least, it would be a more accurate
> emulation of the architecturally defined FPU. If I wanted to be really,
> really pedantic (which I sometimes do), I'd also protect the reserved bits
> that aren't necessarily writable.
Committed a few your ago. Thanks Shane!