v2 - v1:
- Adjusting code structure as suggested by Wu Zhangjin. With this change,
hardware performance event support for loongson2 and rm9000 can be
conveniently implemented by adding and including new files like
perf_event_loongson2.c; Oprofile and Perf for MIPS are now sharing pmu.h;
Naming changes were made to some functions.
- Fixing the generic atomic64 issue reported by David Daney. Currently,
32bit kernel is using the generic version from lib. When Ralf Baechle's
common atomic64 version is ready, this may change.
- Adding raw event support. For more details, please refer to the code
comments for mipsxx_pmu_map_raw_event().
- Adding new software events - PERF_COUNT_SW_ALIGNMENT_FAULTS and
- Fixing some small bugs.
- Adding new comments for the code.
- Making some code style changes.
Deng-Cheng Zhu (4):
- MIPS/Oprofile: extracting PMU defines/helper functions for sharing
- MIPS: in non-64bit kernel, using the generic atomic64 operations for
perf counter support
- MIPS: adding support for software performance events
- MIPS: implementing hardware performance event support
This patch series implemented the low-level logic for the Linux
performance counter subsystem on MIPS, which enables the collection of
all sorts of HW/SW performance events based on per-CPU or per-task.
An overview of this implementation is as follows:
- Using generic atomic64 operations from lib.
- SMVP/UP kernels are supported (not for SMTC).
- 24K/34K/74K cores are implemented.
- Currently working when Oprofile is _not_ available.
- Minimal software perf events are supported.
Tests were carried on the Malta-R board. The mentioned cores and kernel
flavors were tested. For more information, please refer to the particular
Deng-Cheng Zhu (3):
- MIPS: use the generic atomic64 operations for perf counter support
- MIPS: adding support for software perf events
- MIPS: implement hardware perf event support