[Top] [All Lists]

[PATCH 0/3] MIPS performance event support initial version

Subject: [PATCH 0/3] MIPS performance event support initial version
From: Deng-Cheng Zhu <>
Date: Fri, 16 Apr 2010 00:38:31 +0800
Dkim-signature: v=1; a=rsa-sha256; c=relaxed/relaxed;; s=gamma; h=domainkey-signature:received:received:subject:from:to:cc :content-type:date:message-id:mime-version:x-mailer :content-transfer-encoding; bh=kcPhAHKifHLEL21oLKW+xVV1+jJD9XfNr9XBV8GrIb0=; b=k603VkG9MLZjTzKBzF5d7L7IrOSq2E4CCUy8ub7ZTeoVv4AFgsogeJdZII636oE3UM o8T28pzUftHSHjHT9tAoxtWDKxmnasGjjmGbMQUUZ0zmFFbE669uOtZvrC4sVjDGkfn7 Yg3+rKIt/b8At8ptmeSZTv9yvgEuouKLl1Ivs=
Domainkey-signature: a=rsa-sha1; c=nofws;; s=gamma; h=subject:from:to:cc:content-type:date:message-id:mime-version :x-mailer:content-transfer-encoding; b=meqL2bArF7Ot4NPBQr/2LbjlZQEpNPbJTKbuzEA0fSyETk/4TSx0KP0SUJ9y5wuRMO 09lcrO6nUfaWjkjp8vexdn5IP1MB6mvumpQkPl6/oKa/o3HR47UrK7MXgwGwdgMQBOM8 qd/YvnaYr8x7umnrB2SVDS9Sl4nXXnbautkVI=
Original-recipient: rfc822;
This patch series implemented the low-level logic for the Linux
performance counter subsystem on MIPS, which enables the collection of
all sorts of HW/SW performance events based on per-CPU or per-task.

An overview of this implementation is as follows:

- Using generic atomic64 operations from lib.
- SMVP/UP kernels are supported (not for SMTC).
- 24K/34K/74K cores are implemented.
- Currently working when Oprofile is _not_ available.
- Minimal software perf events are supported.

Tests were carried on the Malta-R board. The mentioned cores and kernel
flavors were tested. For more information, please refer to the particular

Deng-Cheng Zhu (3):
- MIPS: use the generic atomic64 operations for perf counter support
- MIPS: adding support for software perf events
- MIPS: implement hardware perf event support

<Prev in Thread] Current Thread [Next in Thread>
  • [PATCH 0/3] MIPS performance event support initial version, Deng-Cheng Zhu <=