|To:||Shmulik Ladkani <email@example.com>|
|Subject:||Re: serial port 8250 messed up after coverting from little endian to big endian on kernel 2.6.31|
|From:||Sergei Shtylyov <firstname.lastname@example.org>|
|Date:||Wed, 28 Oct 2009 14:04:00 +0300|
|Cc:||email@example.com, Florian Fainelli <firstname.lastname@example.org>, email@example.com, linux-mips <firstname.lastname@example.org>, email@example.com|
|References:||<firstname.lastname@example.org> <4AD906D8.email@example.com> <firstname.lastname@example.org> <email@example.com> <firstname.lastname@example.org> <email@example.com>|
|User-agent:||Thunderbird 220.127.116.11 (Windows/20090812)|
Hello. Shmulik Ladkani wrote:
Thanks, Florian. I found the cause of the problem. My board is 32 bit based, so each serial port register is 32bit even only 8 bit is used. So when the board is switched endianess, I need to change the address offset to access the same registers. For example, original RHR register address is 0x8001000 with little endian mode. With big endian, I need to access it as 0x8001003.I assume your uart_port's iotype is defined as UPIO_MEM32.
He wouldn't have to add 3 to the register addresses then.
UPIO_MEM32 makes 8250 access serial registers using readl/writel (which might be a problem for big-endian), while UPIO_MEM makes 8250 access the registers using readb/writeb.
Both may be a problem for big endian.
Maybe you should try UPIO_MEM (assuming hardware allows byte access).
Contrarywise, I think he now has UPIO_MEM and needs to try UPIO_MEM32. WBR, Sergei
|<Prev in Thread]||Current Thread||[Next in Thread>|
|Previous by Date:|
|Next by Date:||Re: kernel panic about kernel unaligned access, David Daney|
|Previous by Thread:|
|Next by Thread:|
|Indexes:||[Date] [Thread] [Top] [All Lists]|