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Re: Got trap No.23 when booting mips32 ?

To: "wilbur.chan" <>
Subject: Re: Got trap No.23 when booting mips32 ?
From: David VomLehn <>
Date: Thu, 22 Oct 2009 13:16:45 -0700
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>And I found that , as a matter of  fact , kernel has registered No.23 as a 
>In trap_init :
>1419          * Only some CPUs have the watch exceptions.
>1420          */
>1421         if (cpu_has_watch)
>1422                 set_except_vector(23, handle_watch);
>So, if a No.23 "signal" happened , kernel should  invoke handle_watch instead.
>But why here kernel complained ? and why kernel entered the IRQ branch
>(do_IRQ) rather than trap branch?

It looks like you are confusing interrupts and exceptions. Exceptions
are a generally a change in the flow of execution of a processor due to
a condition internal to the processor. So, a divide by zero is an a exception.

An interrupt is a change in execution flow due to a device external to the
processor. Keyboards use interrupts to indicate that a key has been

Things can be slightly confusing on the MIPS processor because interrupts
are normally treated as a type of exception. In this case, the exception
type in the ExcCode field of the Cause register is "Int". If your system
uses the external vectored interrupt controller, it will not use an
exception and will instead use an array of interrupt handlers.

In your case, you are getting interrupt request (IRQ) number 23. The message
you are getting indicates that no device driver has told the kernel that
it can handle this interrupt. I suggest that you consult the documentation
for your system to determine which device is using IRQ 23 and ensure that
you have a device driver installed for that device. It is unusual that
a device would cause an interrupt without actions from the device driver;
you might want to investigate the possibility that your system is
incorrectly configured, causing the incorrect IRQ to be generated.

I suggest reading the book, "See MIPS Run Linux" by Dominic Sweetman, to learn
more about the low level details of interrupts and exceptions on the MIPS
processor. For exact details, consult "MIPS32® Architecture For Programmers
Volume III: The MIPS32® Privileged Resource Architecture", available at (you need to sign up for a free account)

David VL

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