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Re: Linux port failing on MIPS32 24Kc

To: David VomLehn <>
Subject: Re: Linux port failing on MIPS32 24Kc
From: "Maciej W. Rozycki" <>
Date: Wed, 8 Jul 2009 20:11:05 +0100 (BST)
Cc: Ralf Baechle <>, joe seb <>,
In-reply-to: <>
Original-recipient: rfc822;
References: <> <> <>
User-agent: Alpine 2.00 (LFD 1167 2008-08-23)
On Wed, 8 Jul 2009, David VomLehn wrote:

> > (Why do people use non-zero starting addresses for memory?  Handling of
> > cache error exceptions is hard enough as it is but with no memory in the
> > low 32k the design idea of the cache architecture that stores relative to
> > $zero can be used goes down the drain and (not considering platform-specific
> > solutions here) only be handled by burning the scarce resource of a TLB
> > entry for an extremly rare event ...)
> (Because hardware people are, uh, insufficiently acquainted with the MIPS
> architecture and don't know what the conventions are. Or why they are that
> way. Then, you're stuck with that architecture forever. Sigh.)

 Many processor architectures have assumptions (i.e. power-up/reset 
defaults) about or even force the existence of RAM at physical address 0.  
With the MIPS architecture actually it has been pretty a recent addition 
in its long history that you are able to get away without.  Given these 
circumstances I am afraid your suspicion sounds like an understatement.

 With the MIPS64r2 architecture though and if you want more than 400+some 
MB of memory, placing RAM from the top of the physical address space seems 
more reasonable to me as you can avoid ROM popping up in the middle then.  

 For the sake of flexibility, including but not limited to ERL operation, 
the virtual-to-physical address translation for the CKSEG0 and CKSEG1 
space could be made configurable via an additional CP0 register.  I'm a 
little bit surprised nobody had thought about it at the time CP0.EBase was 
introduced.  The remapping has to be done anyway and it does not look to 
me as it would take a lot of power and/or silicon space to make it use a 
configurable set of latches rather than a predefined set of hardwired 
logical levels.


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