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Re: [PATCH 1/2] MIPS: Preliminary vdso.

To: Brian Foster <>
Subject: Re: [PATCH 1/2] MIPS: Preliminary vdso.
From: "Kevin D. Kissell" <>
Date: Fri, 24 Apr 2009 09:50:16 +0200
Cc: David Daney <>,
In-reply-to: <>
Original-recipient: rfc822;
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Brian Foster wrote:
On Wednesday 22 April 2009 20:01:44 David Daney wrote:
Kevin D. Kissell wrote:
David Daney wrote:
This is a preliminary patch to add a vdso to all user processes.
Still missing are ELF headers and .eh_frame information.  But it is
enough to allow us to move signal trampolines off of the stack.

We allocate a single page (the vdso) and write all possible signal
trampolines into it.  The stack is moved down by one page and the vdso
is mapped into this space.

Signed-off-by: David Daney <>
Note that for FPU-less CPUs, the kernel FP emulator also uses a user
stack trampoline to execute instructions in the delay slots of emulated
FP branches.  I didn't see any of the math-emu modules being tweaked in
either part of your patch.  Presumably, one would want to move that
operation into the vdso as well.

   As David says, this is a Very Ugly Problem.  Each FP trampoline
  is effectively per-(runtime-)instance per-thread, i.e., there is
  a unique FP trampoline for every dynamic instance of (non-trivial
  non-FP) instruction in an FP delay slot.  This is essentially the
  complete opposite of the signal-return trampoline, which is fixed
  (constant text) for all instances in all threads.

   As such, David's vdso (assuming it's similar to those on other
  architectures (I've not looked at it closely yet)) may not have
  any obvious role to play in moving the FP trampoline('s code?)
  off the user's stack.
I haven't reviewed David's code in detail, but from his description, I thought that there was a vdso page per task/thread.  If there's only one per processor, then, yes, that poses a challenge to porting the FPU emulation code to use it, since, as you observe, the instruction sequence to be executed may differ for each delay slot emulation.  It should still be possible, though.  FP emulation is in itself expensive, and FP branches with live delay slots are a smallish subset of the overall FP instructions to be emulated, so a dynamic scheme to allocate/free slots in a vdso page wouldn't have that dramatic a performance impact, overall.  As the instructions aren't constant, the I-caches would need to be flushed after each dsemul setup, even using a vdso page, but that shouldn't break the fact that one could avoid it for signals, so long as a different cache line within the vdso page is used for signal versus dsemul trampolines.

I'm no longer paid to worry about this stuff - I participate in the mailing list out of habit, as time permits. I don't have any MIPS hardware handy to work with, even if I wasn't busy with totally unrelated stuff.  So my talk is cheap.  You guys can do whatever you want.  I'm just pointing out that, if you want to get rid of executable user stacks, you either have to re-implement FP branch delay slot emulation, or eliminate FPU emulation in the kernel.  If your motivation is really only signal dispatch performance, you can just leave the dsemul stuff on the user stack.


          Kevin K.
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