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Re: [PATCH 18/29] MIPS: Add SMP_ICACHE_FLUSH for the Cavium CPU family.

To: David Daney <>
Subject: Re: [PATCH 18/29] MIPS: Add SMP_ICACHE_FLUSH for the Cavium CPU family.
From: Sergei Shtylyov <>
Date: Fri, 07 Nov 2008 20:59:05 +0300
Cc:, Tomaso Paoletti <>, Paul Gortmaker <>
In-reply-to: <>
Organization: MontaVista Software Inc.
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David Daney wrote:

Signed-off-by: Tomaso Paoletti <>
Signed-off-by: Paul Gortmaker <>
Signed-off-by: David Daney <>

diff --git a/arch/mips/include/asm/smp.h b/arch/mips/include/asm/smp.h
index 0ff5b52..e6f419f 100644
--- a/arch/mips/include/asm/smp.h
+++ b/arch/mips/include/asm/smp.h
@@ -37,6 +37,9 @@ extern int __cpu_logical_map[NR_CPUS];
#define SMP_RESCHEDULE_YOURSELF 0x1 /* XXX braindead */
 #define SMP_CALL_FUNCTION    0x2
+/* Octeon - Tell another core to flush its icache */
+#define SMP_ICACHE_FLUSH    0x4

  Sigh, again new macro without users...

The users are in 01/29 and 04/29, perhaps you missed them.

   Using before defining? Cool. :-]

We are currently touching 82 files. I think the patch set is bisectable for non-octeon targets.

If you would like me to move the Kconfig patch to the end, I can do that. That way you wouldn't have any breakage for octeon if you were to only apply a subset of the patches. Other than that, there are currently no plans to restructure this patch set to try to maintain rigorous define before use ordering.

Maybe it's just me, but IMHO first using the macro and then, 15 patches after that, having a patch that just adds that macro, is going against the common sense...

David Daney

WBR, Sergei

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