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Re: [PATCH 11/36] MIPSR2 ebase isn't just CAC_BASE

To: Chad Reese <>,
Subject: Re: [PATCH 11/36] MIPSR2 ebase isn't just CAC_BASE
From: Brian Foster <>
Date: Wed, 29 Oct 2008 08:38:01 +0100
Cc: "Maciej W. Rozycki" <>, Ralf Baechle <>, David Daney <>, Tomaso Paoletti <>
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On Tuesday 28 October 2008 17:13:44 Chad Reese wrote:
> Maciej W. Rozycki wrote:
> > On Tue, 28 Oct 2008, Ralf Baechle wrote:
> >> Another thing I noticed is that we don't use write_c0_ebase(), so the
> >> firmware better setup this correctly or we crash and burn.  We better
> >> should initialize that right ...
> > 
> >  Well, your version still does not do it...
> From an Octeon perspective, we'd prefer that the kernel not touch ebase
> as we set it in the bootloader. The bootloader sets the proper value
> based on the number of kernels being loaded and which cores the kernel
> is loaded on. This allows some interesting things, like running 16
> kernels each on a different CPU. Although 16 kernels is just a toy
> project, we have a number of customers that run two kernels. They choose
> which cores the kernels run on dynamically at boot time.

 Our system (4KSd-based) also has the bootloader setting EBASE,
 so like Chad, I'd prefer it if the kernel doesn't (always?) do
 it, please.  (We're not doing anything tricky like what Chad
 mentions, it's just that on the SoC in question, it's perhaps
 the easiest way of handling the situation.)


“How many surrealists does it take to   | Brian Foster
 change a lightbulb? Three. One calms   | somewhere in south of France
 the warthog, and two fill the bathtub  |   Stop E$$o (ExxonMobil)!
 with brightly-coloured machine tools.” |

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