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Re: [PATCH 1/1] mips: clear IV bit in CP0 cause if the CPU doesn't suppo

To: "Kevin D. Kissell" <>
Subject: Re: [PATCH 1/1] mips: clear IV bit in CP0 cause if the CPU doesn't support divec
From: Ralf Baechle <>
Date: Wed, 10 Sep 2008 13:50:20 +0200
Cc: Thomas Petazzoni <>,,,
In-reply-to: <>
Original-recipient: rfc822;
References: <> <>
User-agent: Mutt/1.5.18 (2008-05-17)
On Wed, Sep 10, 2008 at 01:11:45PM +0200, Kevin D. Kissell wrote:

> I think it's important to know whether it's U-Boot or Linux that's confused.
> As Thomas Bogendoerfer pointed out, it's not good practice to flip bits  
> whose
> use is unknown to the kernel.  If in fact the CPU in question does  
> support IV,
> was correctly identified as such by U-Boot, but isn't recognized by the MIPS
> Linux kernel, then we ought to fix Linux to recognize the CPU.  If it  
> doesn't
> support IV, but U-Boot thought it did, then U-Boot is broken and ought to
> be fixed.  If you you're stuck with a broken U-Boot for some reason, then
> there ought to be some platform-specific place to put a hack.

What happened is this:

        if (cpu_has_divec) {
                if (cpu_has_mipsmt) {
                        unsigned int vpflags = dvpe();
                } else

but include/asm-mips/mach-qemu/cpu-feature-overrides.h was defining
cpu_has_divec as 0.  It should have been either undefined (for runtime
probing) or 1.  Iow, it was a platform specific bug.

With the large number of wild pre-MIPS32/64 architecture variants around I
feel a little uneasy to just zero the field unless I know that bit 23
really is the IV bit on a particular processor.  Just as an example, the
RM7000 has the IV bit on bit 24, not bit 23 like MIPS32 and the
functionality also differs a little.


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