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[PATCH 1/1] mips: clear IV bit in CP0 cause if the CPU doesn't support d

Subject: [PATCH 1/1] mips: clear IV bit in CP0 cause if the CPU doesn't support divec
From: Thomas Petazzoni <>
Date: Tue, 9 Sep 2008 10:15:25 +0200
Cc:,,, Thomas Petazzoni <>
In-reply-to: <>
Original-recipient: rfc822;
References: <>
When the kernel thinks that the CPU doesn't support the divec feature
(cpu_has_divec is false), reset the corresponding IV bit in the CP0
cause register, so that things will work correctly if the bootloader
had a different idea of the CPU support of the divec feature.

The problem has been found while trying to boot a 2.6.24 kernel for
the Qemu board using U-Boot inside Qemu. For the same CPU type, U-Boot
thinks that divec is supported, and the kernel doesn't. So U-Boot sets
the IV bit, but when the kernel boots and doesn't reset the IV bit,
things break when the first interrupts occur. The Qemu board has been
removed from the kernel in 2.6.25, but the problem might also occur
with other platforms.

Signed-off-by: Thomas Petazzoni <>
Cc: Thiemo Seufer <>
 arch/mips/kernel/traps.c |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 6bee290..8b1e507 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1467,6 +1467,9 @@ void __cpuinit per_cpu_trap_init(void)
                } else
+       else {
+               clear_c0_cause(CAUSEF_IV);
+       }
         * Before R2 both interrupt numbers were fixed to 7, so on R2 only:

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