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Re: [PATCH] mips: Add dma_mmap_coherent()

To: James Bottomley <>
Subject: Re: [PATCH] mips: Add dma_mmap_coherent()
From: Ralf Baechle <>
Date: Thu, 21 Aug 2008 11:20:52 +0100
Cc: Takashi Iwai <>,, Parisc List <>
In-reply-to: <1219255088.3258.45.camel@localhost.localdomain>
Original-recipient: rfc822;
References: <> <1219249633.3258.18.camel@localhost.localdomain> <> <1219255088.3258.45.camel@localhost.localdomain>
User-agent: Mutt/1.5.18 (2008-05-17)
On Wed, Aug 20, 2008 at 12:58:08PM -0500, James Bottomley wrote:

> On Wed, 2008-08-20 at 18:53 +0200, Takashi Iwai wrote:
> > > I'm afraid there are several problems.  The first is that it doesn't do
> > > what you want.  You can't map a coherent page to userspace (which is at
> > > a non congruent address on parisc) and still expect it to be
> > > coherent ... there's going to have to be fiddling with the page table
> > > caches to make sure coherency isn't destroyed by aliasing effects
> > 
> > Hmm...  how bad would be the coherency with such a simple mmap method?
> > In most cases, we don't need the "perfect" coherency.  Usually one
> > process mmaps the whole buffer and keep reading/writing.  There is
> > another use case (sharing the mmapped buffer by multiple processes),
> > but this can be disabled if we know it's not feasible beforehand.
> Unfortunately, the incoherency is between the user and the kernel.
> That's where the aliasing effects occur, so realistically, even though
> you've mapped coherent memory to the user, the coherency of that memory
> is only device <-> kernel.  When the any single user space process
> writes to it, the device won't see the write unless the user issues a
> flush.

Same applied on MIPS.  Some platforms have the additional requirement that
the buffer must not be mapped by the TLB during the DMA operation or bad
things could happen.


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