|To:||Ralf Baechle <firstname.lastname@example.org>|
|Subject:||Re: Adding(?) XI support to MIPS-Linux?|
|From:||"Kevin D. Kissell" <email@example.com>|
|Date:||Wed, 11 Jun 2008 11:35:50 +0200|
|Cc:||"Kevin D. Kissell" <KevinK@paralogos.com>, Brian Foster <firstname.lastname@example.org>, email@example.com, Andrew Dyer <firstname.lastname@example.org>|
|References:||<email@example.com> <firstname.lastname@example.org> <484D856B.email@example.com> <20080611090601.GB19755@linux-mips.org>|
|User-agent:||Thunderbird 22.214.171.124 (Windows/20080421)|
Ralf Baechle wrote:
Do check the documentation. I can't comment officially, but I can observe that, in the hypothetical case where you'd want XI/RI semantics in a 64-bit processor, you might use exactly the same semantics (and therefore the same kernel C code support), but you might want to use different bits for XI/RI in a 64-bit TLB entry than in a 32-bit TLB entry (and therefore different header file definitions).On Mon, Jun 09, 2008 at 09:32:59PM +0200, Kevin D. Kissell wrote:That is correct, though there has long been interest in having XI/RI as an option for non-SmartMIPS cores and I would not be surprised if sooner or later it became more generally available.Cavium has it in their 64-bit core. I haven't verified this in the docs but apparently it is meant to be compatible with the old SmartMIPS ASE for MIPS32.
Regards, Kevin K.
|<Prev in Thread]||Current Thread||[Next in Thread>|
|Previous by Date:||Re: Adding(?) XI support to MIPS-Linux?, Ralf Baechle|
|Next by Date:||Re: [PATCH] : Add support for NXP PNX833x (STB222/5) into linux kernel, Ralf Baechle|
|Previous by Thread:||Re: Adding(?) XI support to MIPS-Linux?, Ralf Baechle|
|Next by Thread:||[patch]modify the MIPS CPU classfication, Chen, Huacai|
|Indexes:||[Date] [Thread] [Top] [All Lists]|