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cache line size for a PCI device

Subject: cache line size for a PCI device
From: Jon Dufresne <>
Date: Mon, 11 Feb 2008 09:59:00 -0500
Original-recipient: rfc822;
Should the cache line size of a PCI device be set by the system BIOS,
the linux kernel, or by the device driver? My device currently has the
cache line size set to 0 on my mips box. Is this a bug with the BIOS or
should I be setting this myself. If I should be setting this myself,
what is the best strategy to determine what the cache line size should
be? Right now the best I can do is mimic the PCI configuration space of
my x86 box, but I'm not sure if this is the best way to go or not.

The same thing goes for latency timer.

Thanks for any help,

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