On Sun, Feb 03, 2008 at 03:16:48AM +0100, Ralf Baechle wrote:
> On Sat, Feb 02, 2008 at 05:08:31PM -0500, Kumba wrote:
> > Thomas Bogendoerfer wrote:
> >> no suprise here. As Ralf already noted cache barrier is a restricted
> >> instruction, it will always cause a illegal instruction when used
> >> in user space. Nevertheless it looks like all IP28 are affected
> >> by the simple exploit. Flo built glibc 2.7 with LLSC war workaround
> >> and this avoids triggering the hang.
> > Ah, didn't know the 'cache' instructions was kernel-mode only. Explains
> > why it survived then :)
> > How does one enable the LLSC war workaround in glibc?
> By modifying the code ;-)
Florian Lohoff firstname.lastname@example.org +49-171-2280134
Those who would give up a little freedom to get a little
security shall soon have neither - Benjamin Franklin
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