On Thu, Jan 10, 2008 at 08:30:16AM -0500, Jon Dufresne wrote:
> > MIPS hardware is different so pci_alloc_consistent is implemented
> > differently. For correct use however this should not matter. Any bugs
> > you may find porting to MIPS were already bugs on x86.
> > (Or in pci_alloc_consistent but I'm optimistic ;-)
> Is there a chance that my platform does not support coherent DMA
> mappings? Or is this unheard of for a MIPs platform?
Hardware coherency for DMA is the exception for low-end embedded MIPS
systems andgiven the CPU address your's is no exception from that.
If your system was supporting hardware coherency for DMA I/O you would
have obtained a cachable CPU address like:
dma_handle=0x026f0000 size=0x00010000 cpu_addr=0x826f0000
A 0x8??????? would be in KSEG0 so cachable.
What hardware are you using anyway?