[Top] [All Lists]

答复: kseg1 uncache access issue

To: "'Ralf Baechle'" <>, "'Thomas Bogendoerfer'" <>
Subject: 答复: kseg1 uncache access issue
From: "lovecentry" <>
Date: Wed, 9 Jan 2008 21:20:11 +0800
Cc: <>
Dkim-signature: v=1; a=rsa-sha256; c=relaxed/relaxed;; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date:mime-version:content-type:content-transfer-encoding:x-mailer:thread-index:in-reply-to:x-mimeole:message-id; bh=V+JzzzEek+/DjBHUQE3kvJRBoXnwXf5JiYv/bjZH1WE=; b=UX7kgTBnF7JLvMHpDW7JyojlfFAP6yxC2s1cVUEkJ2sey7XsXfXxjsPnFRBWZ8s8eoH6ZHDBbQZ9VkeNN+jDWQtK/z4Cr+WpGAjmZKyo40gcn5yJCmpvGIEyDT8WDd0S8fLC5R/32yjb/mjt7CX8XqT5kJ5ZJA09u8jBcOgGF4Q=
Domainkey-signature: a=rsa-sha1; c=nofws;; s=gamma; h=from:to:cc:subject:date:mime-version:content-type:content-transfer-encoding:x-mailer:thread-index:in-reply-to:x-mimeole:message-id; b=PZsX1HAuQZceRSm2NCEj3I8O4v1WV/ox3OZKXGQbyk3E4Ckye9PJ8IiZdqUh6mlpvYghWCCymUbHpYh/5ZmeVaoFlWCxhvaejAqfDRtmMh1u7eBcz/RUCt04Zj4UTptdWNzbrUV5xzeiMCFpskjCMHzNl5vdXX98pEdmCWjGLBU=
In-reply-to: <>
Original-recipient: rfc822;
Thread-index: AchSKI7rL0sXndvHR1mocjxvBlInKgAmcRGQ
Hi gents
        Thanks for your reply. Now I try to implement MIPS R10000
microprcoessor simulation with C language, so many issues still puzzle me
although I have read MIPS R10000 Microprocessor paper introduced by Yeager
1996 more than ten times since last year. 
        As Thomas said, R10K will access directly to dram for those uncached
load/store operations. Which path in the MIPS R10k makes it available? Is
system interface does that stuff? I found it has uncached buffer.
Another issue arises, as system brings up the PC will be assigned to
0xbfc00000 and it need to fetch instructions from dram directly rather than
dram then put first four instructions into decode/remap unit, but from the
MIPS R10000 diagram decode/remap unit only get instructions from ICACHE. How
MIPS R10000 handle this case?


发件人: Ralf Baechle [] 
发送时间: 2008年1月9日 2:59
收件人: Thomas Bogendoerfer
抄送: lovecentry;
主题: Re: kseg1 uncache access issue

On Tue, Jan 08, 2008 at 06:02:06PM +0100, Thomas Bogendoerfer wrote:

> On Wed, Jan 09, 2008 at 12:35:06AM +0800, lovecentry wrote:
> > As we know in mips achitecture if current pc falls into kseg1 segment,
> > memory reference will bypass cache and fetch directly from dram. But for
> > some prcoessor such like mips R10K it has off chip L2 cache. I haven't
> why do you think so ? R10k L2 cache controller is inside CPU and any
> access with uncached attribute will go directly to memory. The only
> systems, where this might be different are systems with caches unknown
> to the cpu. But even those usually obey that uncached accesses are
> going directly to memory.

It should also be mentioned that some R10000 machines do odd stuff with
uncached addresses.

IP27 class machines reuse the entire physical address space several times
to map different things.  The selection of the four uncached address
spaces id done by the uncached attribute which is specified either in
the TLB or or as as bit 59..60 of a virtual address in XKPHYS.

The memory controller of the Indigo 2 R10000 needs to be switched to a
special slower mode to allow uncached accesses first.


<Prev in Thread] Current Thread [Next in Thread>