[Top] [All Lists]

kseg1 uncache access issue

To: <>
Subject: kseg1 uncache access issue
From: "lovecentry" <>
Date: Wed, 9 Jan 2008 00:35:06 +0800
Dkim-signature: v=1; a=rsa-sha256; c=relaxed/relaxed;; s=gamma; h=domainkey-signature:received:received:from:to:subject:date:mime-version:content-type:x-mailer:thread-index:x-mimeole:message-id; bh=PELyFxm5PzJ8bpyBey4ewQLTaqF2L2dyzKngfH4i5zU=; b=oVwHwUOqHnHvqilEYPPCFAJp8Gwy60Ll+Im5Q7jDJoFrfXIRl9tgV1rEqUwUWygglYrTKdR0NBQ/CutRLXR5oE1BTn636XbRDKtww+iT12I9LZDmoWrdWCup6juqEvuvVaYk83IVTSkn0oU8KPwg/9h80Gg+xVxi+JBfHTjFurc=
Domainkey-signature: a=rsa-sha1; c=nofws;; s=gamma; h=from:to:subject:date:mime-version:content-type:x-mailer:thread-index:x-mimeole:message-id; b=Zzi7Mhr9JczG7ahWmPXq13c/C0Zjzg91sCcSg9RW2RHenNBdAUsBG8ohyLRpf/IaF6Me4abT0VkNGYWU5n2R2kmKDbjgLxTEzatv5WhimpWBAKhfbMPph2fGhrj0Cv8Zllszpfsvfsh/fGsdz4DspRHt/w1VHXKkvVrZZbnOa3k=
Original-recipient: rfc822;
Thread-index: AchSFGznFIKi14IwSXqLn9eejUkhaA==


As we know in mips achitecture if current pc falls into kseg1 segment, any memory reference will bypass cache and fetch directly from dram. But for some prcoessor such like mips R10K it has off chip L2 cache. I haven't found any available path which can access dram directly. All memory reference need pass through L2 cache. Does it mean any memory reference in kseg1 will be fetch from L2 cache rather than dram for such system? How does such system design when system software need access kseg1 region? Further more, Kseg2 is used to do memory map for those peripheral so Is there has a particular circuit that routes those access to the appropriate destination.

Any suggestion is highly appreciate!!!



<Prev in Thread] Current Thread [Next in Thread>