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GCC bug affecting MIPS (was Re: SiByte 1480 & Branch Likely instructions

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Subject: GCC bug affecting MIPS (was Re: SiByte 1480 & Branch Likely instructions?)
From: "Kaz Kylheku" <>
Date: Thu, 13 Dec 2007 19:05:20 -0800
In-reply-to: <DDFD17CC94A9BD49A82147DDF7D545C5590D6B@exchange.ZeugmaSystems.local>
Original-recipient: rfc822;
References: <DDFD17CC94A9BD49A82147DDF7D545C5590D6B@exchange.ZeugmaSystems.local>
"Kaz Kylheku" <> wrote on December 07, 2007:
Kaz wrote:
Hi All,

Not really a kernel-related question. I've discovered that GCC 4.1.1
(which I'm not using for kernel compiling, but user space) generates
branch likely instructions by default, even though the documentation
says that their use is off by default for MIPS32 and MIPS64, because

That's because the compiler is not configured correctly. The default CPU
string "from-abi" ends up being used, and so the target ISA is MIPS III.

I managed to root-cause the original problem, and moments ago filed this bug report:

GCC can screw up when doing branch delay slot filling, because in computing register liveness, it makes an incorrectly computed assumption about what registers are clobbered by a CALL_INSN. By unfortunate coincidence, it's possible for an instruction which restores the caller's GP to be wrongly moved into a non-annulled delay slot, wreaking havoc on the fall-through path where GP is in fact used. Jumps and data accesses are then attempted using what is possibly the wrong global offset table.

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