On Wed, 31 Oct 2007 16:13:33 +0000, Ralf Baechle <firstname.lastname@example.org> wrote:
> This one is definately playing with the fire. Or alternatively requires
> detailed knowledge of the pipeline and pipelines tend to change. MIPS
> Technologies does regular maintenance releases of its cores which also
> add features and may change the pipelines in subtle way that may break
> something like this.
Yes, I never think this is robust or guaranteed...
> The only safe but ugly workaround is to change the return from exception
> code to detect if the EPC is in the range startin from the condition
> check in the idle loop to including the WAIT instruction and if so to
> patch the EPC to resume execution at the condition check or the
> instruction following the WAIT.
I'm also thinking of this approach. Still wondering if it is worth to