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Re: [PATCH] enable PCI bridges in MIPS ip32

To: Giuseppe Sacco <>
Subject: Re: [PATCH] enable PCI bridges in MIPS ip32
From: "Maciej W. Rozycki" <>
Date: Thu, 4 Oct 2007 16:03:50 +0100 (BST)
Cc: Ralf Baechle <>,
In-reply-to: <1191508413.10050.26.camel@scarafaggio>
Original-recipient: rfc822;
References: <> <> <> <1191508413.10050.26.camel@scarafaggio>
On Thu, 4 Oct 2007, Giuseppe Sacco wrote:

> I'll provide a new patch tomorrow, using inline functions instead of
> macros. About the maximum number of PCI buses, I used 1 since the ip32
> only have 1 slot. If this maximum value should be changed, please let me
> know.

 You can have more than one bridge on a card.  Or if you have e.g. a 
PCI-HyperTransport bridge on a PCI card, then who knows what may lie 
beyond.  In any case there is no need to do this check here and it is even 
harmful in the sense it just bumps the unnecessary limitation by one 
rather than removing it altogether -- the generic PCI code that we have in 
drivers/pci/ will scan the bus behind the bridge and find out whether 
there are any others and act accordingly.

 In general you need not do any range checking here, even for the root 
bus, unless the host bridge is broken somehow and produces unexpected 
behaviour when an inexistent device is accessed with a configuration 
cycle.  Normally such a transaction should result with a Master Abort and 
be handled gracefully by the originating host bridge.  This is not always 
the case, sometimes because of a flaw in hardware and sometimes because of 
misconfiguration -- unfortunately the quality of bootstrap firmware varies 
and fixing it up requires bridge-specific knowledge, which we sometimes 
have and use (grep for MSC01_PCI_CFG_MAXRTRY_MSK for an example), but 
sometimes we do not.


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