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Re: [Qemu-devel] QEMU/MIPS & dyntick kernel

To: Alan Cox <>
Subject: Re: [Qemu-devel] QEMU/MIPS & dyntick kernel
From: Aurelien Jarno <>
Date: Tue, 02 Oct 2007 22:57:24 +0200
In-reply-to: <>
Original-recipient: rfc822;
References: <> <> <> <>
User-agent: IceDove (X11/20070328)
Alan Cox a écrit :
>> Well on real hardware, the instruction rate and the timer are linked:
>> the timer run at half the speed of the CPU. As the corresponding
>> assembly code is very small, only uses registers and is run in kernel
>> mode, you know for sure that 48 cycles is more than enough.
> What happens on NMI or if you take an ECC exception and scrubbing stall
> off the memory controller while loading part of that cache line of code
> into memory ?

The code returns -ETIME, and the function is run again with the minimum

So as long as you don't have an exception every time, the code works.

  .''`.  Aurelien Jarno             | GPG: 1024D/F1BCDB73
 : :' :  Debian developer           | Electrical Engineer
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