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Re: [PATCH] malta4kec hang in calibrate_delay fix

To: Ralf Baechle <>
Subject: Re: [PATCH] malta4kec hang in calibrate_delay fix
From: yshi <>
Date: Wed, 05 Sep 2007 13:51:23 +0800
In-reply-to: <>
Original-recipient: rfc822;
References: <> <>
在 2007-09-04二的 13:44 +0100,Ralf Baechle写道:
> On Tue, Sep 04, 2007 at 04:52:33PM +0800, yshi wrote:
> > perfmon2 patch changed timer interrupt handler of malta board.
> > When kernel handles timer interrupt, interrupt handler will read 30 bit
> > of cause register. If this bit is zero, timer interrupt handler will
> > exit, won't really handle interrupt. Because Malta 4kec board's core
> > revision is CoreFPGA-3, this core's cause register doesn't implement 30
> > bit, so kernel always read zero from this bit. This will cause kernel
> > hang in calibrate_delay.
> You seem to have defined cpu_has_mips_r2 as 1 in your cpu_features_override.h
> file.  Classic cut'n'paste error I'd guess :-)
I double checked the revision of this board's core. The core is Release
2(cpu_has_mips_r2 is 0x40). So I enabled Release 2 in kernel config. But
kernel still hangs in calibrate_delay. 

I investigated this problem further and found IntCtl register's value is
always zero! So this cause that kernel registers timer interrupt handler
to the wrong IRQ number, because kernel read IntCtl.IPTI bits to
determine timer IRQ number. If I use default IRQ number, kernel will
works well. I printed my board information from YAMON as follows:

Compilation time =              Jul  4 2006  17:12:50
Board type/revision =           0x02 (Malta) / 0x00
Core board type/revision =      0x09 (CoreFPGA-3) / 0x01
System controller/revision =    MIPS SOC-it 101 EC-32 / 1.3  SDR-FW-1:1
FPGA revision =                 0x0001
MAC address =                   00.d0.a0.00.04.e1
Board S/N =                     0000000961
PCI bus frequency =             25 MHz
Processor Company ID/options =  0x01 (MIPS Technologies, Inc.) / 0x00
Processor ID/revision =         0x90 (MIPS 4KEc) / 0x68
Endianness =                    Big
CPU/Bus frequency =             33 MHz / 33 MHz
Flash memory size =             4 MByte
SDRAM size =                    32 MByte
First free SDRAM address =      0x800b6980

According MIPS32 Release 2 specification, IntCtl.IPTI bits should not be
zero, at least 2 and it's readonly. So, is my board defective or an old
version? Thanks.

Best Regards,
Yang Shi
>   Ralf

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