|To:||"Maciej W. Rozycki" <firstname.lastname@example.org>|
|Subject:||Re: Modpost warning on Alchemy|
|From:||Sergei Shtylyov <email@example.com>|
|Date:||Thu, 02 Aug 2007 18:15:50 +0400|
|Cc:||Ralf Baechle <firstname.lastname@example.org>, email@example.com|
|Organization:||MontaVista Software Inc.|
|References:||<20070801115231.GA20323@linux-mips.org> <46B07B36.firstname.lastname@example.org> <Pine.LNX.4.64N.email@example.com> <46B086EB.firstname.lastname@example.org> <46B0880B.email@example.com> <Pine.LNX.4.64N.firstname.lastname@example.org> <46B0AA74.email@example.com> <Pine.LNX.4.64N.firstname.lastname@example.org> <46B0B6B4.email@example.com> <Pine.LNX.4.64N.firstname.lastname@example.org> <46B0BD99.email@example.com> <Pine.LNX.4.64N.firstname.lastname@example.org> <46B1D2F7.email@example.com> <Pine.LNX.4.64N.firstname.lastname@example.org>|
|User-agent:||Mozilla/5.0 (X11; U; Linux i686; rv:1.7.2) Gecko/20040803|
Maciej W. Rozycki wrote:
It does not help too much with a 32-bit virtual address space indeed. Though I gather it has to be very sparsely populated as 16MiB is enough tocover the whole configuration space of a single PCI bus tree. Thus it has
Hm, maybe 16 MiB would be enough indeed, as the Alchemy CPUs are known to not support bus masters behind PCI bridges...
That is unrelated -- for configuration accesses (assuming the basic
I mean who needs crippled subordinate busses? ;-)
configuration space) you need: 8 bits for the bus number + 5 bits for the device number + 3 bits for the function number + 8 bits for the register number. The total is 24 bits.
Yeah, that the format of type 1 cycles.
It is up to hardware to sort it out and put the right bits on the bus.
Unfortunately, Alchemy designers were too lazy to implement a simple translation scheme for type 0 cycles. They probably though that with 36-bit bus the may not limit themselves... :-)
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