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CACHE instruction on MIPS32 24KE

Subject: CACHE instruction on MIPS32 24KE
From: "Mohamed Bamakhrama" <>
Date: Thu, 12 Jul 2007 18:14:29 +0200
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Original-recipient: rfc822;
Hi list,
I have one question regarding the cache instruction. In the MIPS32
24KE software user's manual (page 317), it mentions that it is
possible to perform "fetch & lock" operation on a given cache line.
I am developing a driver for 2.4.31 kernel and I want to be able to
lock some "hot spots" inside the instruction cache to maximize the
throughput. Nevertheless, the manual states that if all the 4-ways of
the cache set were locked, then the core will just replace one of
them. So theoretically, the core should overwrite one of the ways in
case of the first collision and then use that overwritten line for
subsequent collisions. What I observe in my program is different. The
# of I$ misses is the same. I tried to move the locking code around
and when I did it just before the basic block I got an improvement of
20% only!!
My questions are:
1) Is there any parts in the kernel which unlocks the I$ lines under
some circumstances?
2) Is there anyone who worked with the cache instruction under MIPS
before and have any ideas about this behaviour?

Here is the macro used for cache locking:

***** BEGIN CODE *****

#define LOCK_IN_CACHE(address, lines)   \
        asm volatile (  ".set      mips32 \n" \
                        ".set      noreorder \n"      \
                        "lock_me_" #address ": \n"  \
                        "  cache   0x1C, 0x00(%0) \n" \
                        "  addiu   %z0, %z0, 0x20 \n" \
                        "  sub     %z1, %z1, %z3  \n" \
                        "  bgez    %z1, lock_me_" #address " \n"    \
                        ".set      mips0 \n"  \
                        : : "Jr" (&address),      \
                        "Jr" (lines), "Jr" (0), "Jr" (1));

***** END CODE *****

Best Regards,


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