Franck Bui-Huu wrote:
Actually I'm wondering if we shouldn't create a new file
"arch/mips/kernel/time2.c" which will be a complete rewrite of the
old one (interrupt handler, function pointers, clocksource,
clockevent). This file would be the future replacement of the old
time.c. This new file would be used only if the board have been
updated accordingly. That may help to migrate...
We've been there and done that -- for George Anzinger's HRT. :-)
Another issue I have is to implement clockevent set_mode() method. You
left it empty but I think we need at least to shut down the timer
interrupt when setting the clock event device. Strangely I haven't
found a "generic" way to stop them through cp0. Have I missed
You can mask the count/compare interrupt in the status register like any
other interrupt. Keep in mind that on many CPUs this interrupt is
shared with the performance counter interrupt so cannot always be
Well this interrupt could be shared with other devices too, couldn't it ?
If so only the board code can disable it.
There is no other disable bit for this interrupt than the IE bit in the
status register. So it may just have to be ignored.
That would mean we can't have a tickless system in these cases, wouldn't
No, it doesn't. Even on dyntick kernels, interrupts do happen several
times a second. Dynticks have nothing to do with disabling timer interrupts...