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Re: replacing synthesized tlb handlers with older ones

To: "Kevin D. Kissell" <>
Subject: Re: replacing synthesized tlb handlers with older ones
From: Ralf Baechle <>
Date: Sun, 4 Jun 2006 18:51:29 +0100
Cc: Prasad Boddupalli <>,
In-reply-to: <01b401c68678$98199a10$10eca8c0@grendel>
Original-recipient: rfc822;
References: <> <01b401c68678$98199a10$10eca8c0@grendel>
User-agent: Mutt/
On Fri, Jun 02, 2006 at 09:13:11PM +0200, Kevin D. Kissell wrote:

> The TLB refill handler behavior for 1 CPU is fundamentally
> different than for SMP.  In the uniprocessor case, the page
> table origin is implicit, whereas in SMP it needs to be indexed
> by some per-CPU value, typically maintained in the Context
> register.  Pre-synthesed kernels set up up so that the Context
> value would be shifted left 23 bits, then right by 2 bits, to generate
> an offset.  The newer system eliminates the right shift by ensuring
> that the CPU index is stored in a pre-scaled form, and that bits
> 23 and 24 are zero.  So you can't just drop the old code into
> the newer kernel, unless you also change the setup of Context.
> A single CPU would work, because 0 == 0, otherwise...
> Try nuking those right shifts.

And beyond that, the old ones hardly made any reasonable attempt at
getting TLB hazard handling right, so depending on hardware they will
blow up.


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