I have a question regarding the following warning in the arch/mips/kernel/irq_cpu.c.
What is the reason for this comment and in case it is not SMP safe, what are the changes needed to make it SMP safe?
* Almost all MIPS CPUs define 8 interrupt sources. They are typically
* level triggered (i.e., cannot be cleared from CPU; must be cleared from
* device). The first two are software interrupts which we don't really
* use or support. The last one is usually the CPU timer interrupt if
* counter register is present or, for CPUs with an external FPU, by
* convention it's the FPU exception interrupt.
* Don't even think about using this on SMP. You have been warned.
* This file exports one global function:
* void mips_cpu_irq_init(int irq_base);