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Re: Timer Interrupt

To: Linux MIPS <>
Subject: Re: Timer Interrupt
From: Bharathi Subramanian <sbharathi@MidasComm.Com>
Date: Fri, 27 Jan 2006 14:02:36 +0530 (IST)
In-reply-to: <00e501c61b75$a5f0c0a0$10eca8c0@grendel>
Original-recipient: rfc822;
On Tue, 17 Jan 2006, Kevin D. Kissell wrote:

> You were on the right track when you tried hacking mips_timer_ack(),
> but note that both cycles_per_jiffy and mips_hpt_frequency end up
> being used in Count-based time calculations.

I fixed the CPU Clock down and Timer interrupt problem like this:

static void c0_timer_ack(void)
  int count;
 /* Bharathi: To maintain the Timer in clock down mode.
  * cpu_clk_change is set by PMU Driver */

 if(test_and_clear_bit(0, &cpu_clk_change))
   READ_REG( PMU_CLKMODE, cpu_clk_div);
   /* Divide the orginal timer count */
   my_cycles_per_jiffy = cycles_per_jiffy >> (cpu_clk_divA);
 /* Ack this timer interrupt and set the next one. */
 expirelo += my_cycles_per_jiffy;

 /* Check to see if we have missed any timer interrupts. */
 count = read_c0_count();

 if ((count - expirelo) < 0x7fffffff) {
    expirelo = count + my_cycles_per_jiffy;


0. cpu_clk_change is global, static and exported to access in PMU Drv.

1. In time_init(), set my_cycles_per_jiffy = cycles_per_jiffy to
   handle initial state.

2. If needed, Change the SDRAM Refresh Rate during clk dwn.

3. Force few uSec delay after clock-up for smooth & stable transition.

4. I am NOT an expert in Kernel/MIPS. Feel free to correct me.

Kindly CC me.

Thanks :)
Bharathi S

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