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Re: [RFC] Optimize swab operations on mips_r2 cpu

To: Franck <>
Subject: Re: [RFC] Optimize swab operations on mips_r2 cpu
From: Ralf Baechle <>
Date: Wed, 25 Jan 2006 15:04:04 +0000
Cc: "Kevin D. Kissell" <>,
In-reply-to: <>
Original-recipient: rfc822;
References: <> <> <> <> <> <>
User-agent: Mutt/
On Wed, Jan 25, 2006 at 03:32:22PM +0100, Franck wrote:

> > We have CPU_MIPS32_R1, CPU_MIPS32_R2, CPU_MIPS64_R1, CPU_MIPS64_R2.
> > Based on those we also define CPU_MIPS32, CPU_MIPS64, CPU_MIPSR1,
> > and CPU_MIPSR2 as short cuts.
> >
> hm I should have missed something, but what about CPUs which have
> their own CPU_XXX (different form CPU_MIPS32_R[12]) and which are a
> mips32-r2 compliant for example ? (I'm thinking of 4KSD for example)

The 4KSD is still a MIPS32 processor - just one with an ASE.

The real bug here - and what's causing your confusion - is that the
processor configuration is mixing up all the architecture variants
(MIPS I - IV, MIPS32 and MIPS64 R1/R2, weirdo variants ...) and the
processor types.  Example: 4K, 4KE, 24K, 24KE, 34K, AMD Alchemy are all
MIPS32 (either R1 or R2).  R4000, R4400, R4600 are all MIPS III.  But
what we actually offer in the processor configuration is R4X00, MIPS32_R1,


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