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Re: Au1550 system bus masters issue

To: David Sanchez <>, Linux MIPS Development <>
Subject: Re: Au1550 system bus masters issue
From: Sergei Shtylylov <>
Date: Mon, 05 Dec 2005 14:36:05 +0300
In-reply-to: <>
Organization: MostaVista Software Inc.
Original-recipient: rfc822;
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David Sanchez wrote:

I notice the following issue in the specification update (v31420) of the

"System bus masters (USB host, PCI, MAC0, MAC1, DDMA) may receive stale

System bus masters (USB host controller, PCI controller, MAC0, MAC1,
DDMA controller), when performing
coherent reads, may incorrectly receive stale data from memory instead
of valid modified data from the Au1
data cache. If the request for data arrives within a 3-clock window
prior to the cache line castout to memory,
the cache snoop response is incorrect and stale data is retrieved from
memory instead of the correct data from
the cache. The cache line castout then completes, and memory is updated.
Cache/memory data is not corrupted, but the specific bus read in not

Affected Step

Do not enable cacheable master reads if the core modifies data in cache.

Not Fixed"

Does somebody known if the linux kernel 2.6.10 integrates this
workaround ?

   Mainly as CONFIG_DMA_NONCOHERENT defined. USB OHCI and PCI still have
coherency enabled but as the cache hits prone to errata shouldn't happen due to the CONFIG_DMA_NONCOHERENT, it's probably not a problem (enabling coherency in Ethernet driver however makes the kernel non-bootable. USB host controller (and probably not only it, I'm too lazy to re-check ;-) is still prone to other errata on stepping AB though, see this thread:

I'm gonna rework the patch and resubmit.


WBR, Sergei

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