FWIW, the 4KSc is a strict superset of the 4Kc (anticipating
*some* of the Release 2 features, but not requiring them to be
used) and the 4KSd is a strict superset of the 4KE. I would
not recommend configuring CPU_MIPS32_R2 for the 4KSc.
Both of these cores have "SmartMIPS" MMUs, which allow for
orthogonal control of Read/Write/Execute permissions on pages,
using a couple of additional bits at the top of the EntryLo
registers - which in turn limit the maximum usable physical
address space. They also allow for variable granularity of
the PageMask register, to support 1K pages. But these features
are all done in a way that's backward-compatible with MIPS32,
and the default reset behavior makes them look like 4Kc/4KEc.
They also have some physical security and cryptography accelleration
features, some of which use extended CPU state that would
require some kernel context management support if anyone wanted
to actually use them in Linux applications. The real point of
having a CPU_4KSC config flag would be to enable building-in
I'm being a teeny bit vague about this, because I'm not 100%
certain that all the details of "SmartMIPS" have been published.
Maciej W. Rozycki wrote:
On Tue, 4 Oct 2005, Franck wrote:
This patch adds support for both 4ksc and 4ksd cpus. These cpu are
mainly used in embedded system such as smartcard or point of sell
devices as they provide some extra security features.
Please send patches inline.
Apart from the change to "arch/mips/kernel/cpu-probe.c", which is useful,
what's the benefit of the changes? Specifically how is selecting e.g.
"CPU_4KSC" meant to be different from "CPU_MIPS32_R2"? Do you want to
make GCC tune your code according to a specific's CPU pipeline
description? If so, then it should probably be done a bit differently and
there is actually no need to differentiate between specific members of the
Signed-off-by: Franck <firstname.lastname@example.org>
You should rather use your real name here. [Hmm, why am I responding to
an anonym in the first place?...]