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Re: [patch 4/5] SiByte fixes for 2.6.12

To: "Maciej W. Rozycki" <>
Subject: Re: [patch 4/5] SiByte fixes for 2.6.12
From: Andy Isaacson <>
Date: Thu, 23 Jun 2005 15:27:09 -0700
In-reply-to: <>
Original-recipient: rfc822;
References: <> <> <> <>
User-agent: Mutt/1.4.2i
On Thu, Jun 23, 2005 at 04:11:51PM +0100, Maciej W. Rozycki wrote:
> On Thu, 23 Jun 2005, Andy Isaacson wrote:
> > The code looks like it's structured to be able to be compiled with
> > support for multiple CPUs, say, r4k and SB1; using #error would seem to
> > prevent that.
> > 
> > With the code as currently structured, you don't know it's going to be a
> > noop until runtime comes along and cpu_has_4ktlb is true...
>  Well, I've had a look at the code and it's such a mess.  Obviously 
> calling ld_mmu_r4xx0() (or any of the other variants) should not be 
> compiled conditionally and more specific cases, i.e. based on PRId values 
> should take precedence.  I'll see if I can make it better.

I certainly won't argue with a cleanup of arch/mips/mm/cache.c, that
code has annoyed me from first laying eyes on it...


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