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Re: Dubious MIPS kernel SMP Structures

To: Ralf Baechle <>
Subject: Re: Dubious MIPS kernel SMP Structures
From: "Kevin D. Kissell" <>
Date: Wed, 17 Nov 2004 18:07:39 +0100
Cc: Linux-MIPS Mailing List <>
In-reply-to: <>
Original-recipient: rfc822;
References: <006d01c4ccba$36a43110$10eca8c0@grendel> <>
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Ralf Baechle wrote:

[snip of lots of cool historical explanations]

> As you found the IP27 code doesn't properly setup these mappings anymore;
> partly because it's SMP initialization code is twisted to the point
> where nobody understands it anymore.  Partly also because the systems
> we used as SGI were too large to leave CPU numbers unused :)
> Honestly no idea why the Sibyte code is using that mapping stuff.  The
> Sibyte firmware is always launching the kernel on CPU 0 anyway so we have
> the case of either only CPU 0 or both CPU 0 and CPU 1 which means the
> mapping would always be a 1:1 mapping.
> For most simple SMP or ccNUMA configurations assuming a 1:1 mapping is
> reasonable.  For some uniprocessor configurations where a uniprocessor
> kernel is running on a single processor other than processor number 0 on
> a multiprocessor platform this also may be useful.

But my question is really one of why it is that the platform-independent
MIPS kernel code needs/needed to know anything about physical CPU numbers?
Naively, I would have thought that any such mapping would be burried
in the platform code, and that the architectural kernel code would
simply invoke (possibly null) platform-level functions that do whatever
mapping of logical 0...N CPU numbers to bizarre mesh node numbers might
be necessary. As it stands, people who have no need to do mapping (SiByte,
PMC-Sierra, and stuff we're doing at MIPS around MIPS MT) are mindlessly
replicating code to set up 1:1 mappings that will never (in the PMC-Sierra
and MIPS cases) be referenced.


                Kevin K.

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