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Re: TLB dimensioning

To: Johannes Stezenbach <>, Dominic Sweetman <>, Emmanuel Michon <>,
Subject: Re: TLB dimensioning
From: Ralf Baechle <>
Date: Thu, 2 Sep 2004 12:31:37 +0200
In-reply-to: <>
Original-recipient: rfc822;
References: <> <> <>
User-agent: Mutt/1.4.1i
On Thu, Sep 02, 2004 at 12:19:57PM +0200, Johannes Stezenbach wrote:

> Hm, the MIPS32 4K Processor Core Family Software User's Manual says:
> "...the 4Kc core contains a 3-entry instruction TLB (ITLB), a 3-entry
> data TLB(DTLB), and a 16 dual-entry joint TLB (JTLB) with variable page
> sizes."
> What exactly does that mean, and how does it rate performancewise?
> I'm just curious ;-)

The idea behind ITLB and DTLB is to enable parallel TLB lookups for
instruction and data translations in ITLB and DTLB yet not having to make
dual or even more ported JTLB.  ITLB and DTLB are entirely managed in
hardware and therefore not visible [1] to the OS software and as such
not part of the architecture; only the JTLB is and it's what's usually
meant when documentation or we on this list are speaking of the TLB.
Probably most MIPS implementations since at least the R4600 had ITLB and


[1] Except possibly during hazards but your supposed to avoid them :-)

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