On Tue, Jul 13, 2004 at 12:25:37AM +0200, Kevin D. Kissell wrote:
> Hmm. On closer examination, there *is* a bug in the current
> in that it computes its cache flush loop for the I-cache based on the D-cache
> line size.
> Those line sizes are *usually* the same. By any chance are they different
> for the
> TX49 family? If the icache line is longer than the dcache line, there should
> be no
> functional problem, just some wasted cycles. But if the dcache line were,
> twice the length of the Icache line, only half of the icache lines would be
Whoops. Fixing ...